Making Through-Silicon Via (TSV): How the realisation happens?

Introduction

The rapid growth of artificial intelligence (AI) has created a new challenge for semiconductor companies – moving massive amounts of data between processors and memory at extremely high speeds.

While GPUs have become more powerful, traditional DRAM memory has struggled to keep pace, creating a bottleneck in AI performance.

Through-Silicon Via (TSV) technology addresses this challenge by enabling High Bandwidth Memory (HBM), where multiple DRAM chips are stacked vertically and connected through microscopic electrical pathways.

Why TSV Was Needed for DRAM and HBM

Traditional DRAM follows a 2-dimensional design, where memory chips are placed separately and connected through a circuit board. This limits data transfer speed because signals must travel longer distances.

AI workloads require much higher memory bandwidth. Large AI models contain billions of parameters and continuously exchange data between processors and memory. HBM solves this by stacking multiple DRAM layers vertically, while TSV provides direct high-speed communication between these layers.

For example, SK hynix’s 12-layer HBM3E product delivers 36GB capacity and 1.18 TB/s bandwidth, supporting the demanding requirements of modern AI accelerators. (SK hynix)

How TSV Technology Works

The TSV manufacturing process involves four major steps:

1. Creating microscopic pathways
Tiny vertical holes are etched through silicon wafers using deep reactive ion etching. These vias are only a few micrometres wide but require extremely high precision.

2. Creating electrical connections
The vias are insulated to prevent leakage and filled with copper to form conductive pathways between DRAM layers.

3. Stacking DRAM layers
Individual memory dies are thinned, aligned, and stacked vertically. Advanced bonding techniques connect multiple layers, with current HBM designs typically using 8–12 DRAM layers.

4. Testing and packaging
The completed HBM package undergoes extensive testing because defects in even a small number of connections can impact performance and reliability.

Challenges and Future of TSV

The biggest challenges linked to TSV are as follows:

a) Manufacturing is achieving high production yield. Thousands of connections must function reliably within a single HBM package, making defect control extremely important

b) Thermal management is another challenge because stacking multiple layers increases heat concentration

c) Additionally, TSV-based HBM requires specialised equipment and advanced packaging processes, increasing manufacturing costs

As AI models continue to expand, demand for higher memory bandwidth will keep growing. Future technologies such as HBM4 will require improved TSV designs, better thermal solutions, and more advanced chip integration.

TSV represents a major shift in semiconductor innovation – from simply making chips smaller to building powerful computing systems by stacking and connecting multiple chips together.

References for Further Reading

1. SK hynix – HBM Technology and TSV Development
   https://news.skhynix.com/
2. TSMC – Advanced Packaging Technologies
   https://www.tsmc.com/
3. Samsung Semiconductor – HBM and Advanced Packaging
   https://semiconductor.samsung.com/
4. Semiconductor Industry Association – Advanced Packaging Trends
   https://www.semiconductors.org/